The present invention relates to a structure of a semiconductor device which is obtained by forming it in large numbers on a semiconductor wafer and subsequent dicing and separation.
It is general that, when fabricating a semiconductor device (various kinds of transistors and various kinds of diodes), a large number of individual semiconductor dies are formed in array on a large semiconductor wafer (semiconductor substrate) and, by finally cutting scribe lines existing between the semiconductor dies (dicing the semiconductor wafer), the semiconductor dies are obtained as individually separated ones. The dicing is generally performed using a disk-shaped dicing blade in rotation, which intersects with the semiconductor wafer. At that time, there may occur chipping at an end portion (on a side having been in contact with the dicing blade) within the diced and separated semiconductor die. The chipping is caused by a crack generated in the semiconductor wafer during the dicing. In the semiconductor die, an area to perform actual electrical operation (operation area) is located apart from the end portion, but chipping exerts malfunction on the operation and reliability when it becomes large. Wide bandgap group-III nitride compound semiconductors are widely used as materials for power semiconductor devices and light emitting devices, but it is general that a crack occurs more easily in the group-III nitride compound semiconductors represented by GaN than in silicon and the like, during their processing, and accordingly, chipping occurs easily particularly in the group-III nitride compound semiconductors.
The malfunction such as chipping and cracking can be reduced by locating the operation area sufficiently apart from an end portion cut in the above-described way, in the semiconductor die. However, in that case, a practical area of individual semiconductor die is increased, accordingly the number of semiconductor dies obtained from one semiconductor wafer is reduced, and therefore cost reduction of the semiconductor dies is difficult.
In view of the above-described situation, it is described in JP-2017-41616 (A) that, by removing, at the side of an edge in individual semiconductor dies (semiconductor devices), an oxide layer (silicon oxide layer) formed on the surface, and making an end portion of the oxide layer have a tapered shape (bevel-cut shape), chipping occurrence and crack development toward the semiconductor die side can be suppressed. In that case, the bevel-cut shape of the oxide layer can be formed by mechanical processing and the like.
In the technology described in JP-2017-41616 (A), the bevel-cut shape is formed over the entire periphery of the semiconductor die, but it takes long time to perform such mechanical processing precisely over the entire periphery in every semiconductor die. Further, in the technology, the mechanical processing needs to be performed only on an edge of the oxide layer but, if the semiconductor substrate is damaged in the processing, malfunction on electrical characteristics and reliability of semiconductor dies is generated.
For these reasons, it has been difficult to achieve, by the technology described in JP-2017-41616 (A), a low cost semiconductor device in which occurrence of chipping and a crack during dicing is suppressed.
The present invention has been made in view of the above-described issue, and accordingly is aimed at providing an invention to resolve the issue.